1. Field of the Invention
The embodiments discussed herein are related to a semiconductor integrated circuit device.
2. Description of the Related Art
High-voltage integrated circuit devices (HVICs) of an element isolation system utilizing high-voltage junction are semiconductor integrated circuit devices that drive and turn on/off switching power devices making up an upper arm of a bridge circuit for power inversion (DC-AC conversion) such as a pulse width modulation (PWM) inverter. An HVIC has a means of detecting overcurrent and temperature during times of malfunction of the switching power device and thereby affords higher performance. Further, an HVIC enables a smaller size and a lower cost since differing potentials are not isolated by a transformer, a photocoupler, etc.
A conventional HVIC connection configuration will be described taking, as an example, an HVIC driving an insulated gate bipolar transistor (IGBT) used as a switching power device in power conversion equipment such as an inverter. FIG. 10 is a circuit diagram of a connection configuration of a high-voltage integrated circuit device. FIG. 10 depicts a power conversion device including a half bridge circuit with two switching power devices (IGBTs 114, 115) connected in series.
The power conversion device depicted in FIG. 10 includes an HVIC, low-voltage power sources (first and second low-voltage power sources) 112, 113, the IGBTs 114, 115, free wheel diodes (FWDs) 116, 117, an L-load (inductive load) 118, and a capacitor 119. This power conversion device alternately turns on the IGBT 115 and the IGBT 114 acting as an upper arm and a lower arm, respectively, of the half bridge circuit whereby output at a high potential or a low potential is alternately output from a Vs terminal 111 acting as an output terminal, thereby supplying AC power to the L-load 118.
In particular, the HVIC is a driving element complementarily turning on/off the IGBT 115 and the IGBT 114 acting as the upper arm and the lower arm, respectively, of the half bridge circuit. If the output from the Vs terminal is at a high potential, the HVIC operates the IGBTs 114, 115 to turn on the upper-arm IGBT 115 and turn off the lower-arm IGBT 114. On the other hand, if the output from the Vs terminal 111 is at a low potential, the HVIC operates the IGBTs 114, 115 to turn off the upper-arm IGBT 115 and turn on the lower-arm IGBT 114.
During an operation period, the HVIC outputs a gate signal of the lower-arm IGBT 114 from an L-OUT by using a potential of a GND (grounding potential) as a reference. The HVIC outputs a gate signal of the upper-arm IGBT 115 from an H-OUT by using the potential of the Vs terminal 111 as a reference. The HVIC includes a level shift function (a level shifter circuit (a level-up circuit and a level-down circuit) not depicted) so as to output the gate signal of the upper-arm IGBT 115 from the H-OUT by using the potential of the Vs terminal 111 as a reference.
The level-up circuit increases the logic level of a signal input from an H-IN and generates the gate signal of the IGBT 115. The level-down circuit inputs an abnormality signal 110 related to overheating or overcurrent of the IGBT 115, forms an alarm signal based on the abnormality signal 110 and decreases the level of this alarm signal. The H-IN is connected to a gate of a complementary metal oxide semiconductor (CMOS) circuit (a low-side circuit unit not depicted) that is a peripheral circuit on the low side (upstream) of the level-up circuit. The H-IN is an input terminal receiving an input signal transferred to the low-side circuit unit upstream from the level-up circuit.
The H-OUT is connected to an output terminal of a CMOS circuit (high-side circuit not depicted) that is a peripheral circuit on the high side (downstream) of the level-up circuit. The H-OUT is connected to a gate of the upper-arm IGBT 115 disposed downstream from the HVIC. The H-OUT is an output terminal supplying a gate signal to the IGBT 115. An L-IN is an input terminal receiving an input signal transferred to a CMOS circuit that supplies a gate signal to the IGBT 114. The CMOS circuit supplying the gate signal to the IGBT 114 generates the gate signal of the IGBT 114 based on a logic level of a signal input from the L-IN.
The L-OUT is connected to an output terminal of the CMOS circuit that supplies a gate signal to the IGBT 114. The L-OUT is connected to a gate of the lower-arm IGBT 114 disposed downstream from the HVIC. The L-OUT is an output terminal supplying the gate signal to the IGBT 114. An ALM-IN indicates an input of the abnormality signal 110 of the IGBT 115. The abnormality signal 110 is input to a detection circuit (not depicted) that forms the alarm signal based on the abnormality signal 110. An ALM-OUT is connected to an output terminal of a CMOS circuit (low-side circuit not depicted) that is a peripheral circuit on the low side (downstream) of the level-down circuit. The ALM-OUT is an output terminal that outputs the alarm signal for which the level has been decreased by the level-down circuit.
An H-VDD is a terminal connected to the high-potential side of the low-voltage power source 113 that uses a potential of a Vs as a reference. An L-VDD is a terminal connected to the high-potential side of the low-voltage power source 112 using the potential of the GND as a reference. The Vs is a terminal having an intermediate potential (floating potential) varying from a potential of a high-potential-side Vss of a high-voltage power source (main circuit power source) to the potential of the GND and has the same potential as the Vs terminal 111. The GND is a ground (grounding) terminal. The low-voltage power source 112 is a low-side drive power source connected between the L-VDD and the GND of the HVIC. The low-voltage power source 113 is a high-side drive power source connected between the H-VDD and the Vs of the HVIC. In the case of a bootstrap circuit system, the low-voltage power source 113 is made up of an external capacitor (not depicted) charged by an external bootstrap diode (not depicted) connected between the L-VDD and the H-VDD.
The IGBT 114 has an emitter connected to the GND on the low-potential side of the high-voltage power source and has a collector connected to an emitter of the IGBT 115. The IGBT 115 has a collector connected to the high-potential-side Vss of the high-voltage power source. The IGBTs 114, 115 are respectively connected to FWDs 116, 117 in anti-parallel. A connection point between the collector of the IGBT 114 and the emitter of the IGBT 115 (i.e., an output terminal of the half bridge circuit) is connected to the Vs terminal 111. The Vs terminal 111 is connected to the Vs of the HVIC and the L-load 118. The L-load 118 is AC resistance (reactance), for example, a motor or an illumination, operating by using a bridge circuit formed by combining the half bridge circuits (the IGBTs 114, 115). The capacitor 119 is connected between the L-VDD and the GND.
The level shifter circuit (the level-up circuit and the level-down circuit) of the HVIC will be described. FIG. 11 is a circuit diagram of the level-up circuit. FIG. 12 is a circuit diagram of the level-down circuit. FIGS. 11 and 12 include CMOS circuits that transfer input signals to the level shifter circuit and CMOS circuits that transfer output signals of the level shifter circuit to downstream peripheral circuits of the level shifter circuit. An H-IN, an H-OUT, an ALM-IN, an ALM-OUT, an H-VDD, an L-VDD, a Vs, and a GND depicted in FIGS. 11 and 12 respectively correspond to the H-IN, the H-OUT, the ALM-IN, the ALM-OUT, the H-VDD, the L-VDD, the Vs, and the GND depicted in FIG. 10.
A level-up circuit 210 depicted in FIG. 11 includes an n-channel insulated gate field effect transistor (Metal Oxide Semiconductor Field Effect Transistor (MOSFET)) 211, a level shift resistor 212, and a diode 213. The level-up circuit 210 is necessary when the upper-arm IGBT 115 of the half bridge circuit is of an n-channel type. The drain of the re-channel MOSFET 211 is connected to one end of the level shift resistor 212 and the source is grounded. The n-channel MOSFET 211 has a built-in body diode 214 connected in anti-parallel to the n-channel MOSFET 211. A connection point between the n-channel MOSFET 211 and the level shift resistor 212 is an output unit 215 of the level-up circuit 210.
The other end of the level shift resistor 212 is connected to the H-VDD. The diode 213 is connected in parallel to the level shift resistor 212. The diode 213 has a function of preventing the level shift resistor 212 from generating heat and being destroyed by the heat generated when the potential of the H-VDD becomes considerably lower than the potential of the GND (when excessive negative surge voltage (hereinafter, negative surge voltage) is applied). The diode 213 has a function of preventing excessive voltage from being applied to a gate of a CMOS circuit of a high-side circuit unit 217 described later when overvoltage is applied to the H-VDD during on-operation of the n-channel MOSFET 211. Typically, a Zener diode is frequently used for the diode 213.
A low-side circuit unit 216 and the high-side circuit unit 217 are disposed upstream and downstream from the level-up circuit 210 as peripheral circuits of the level-up circuit 210. Both the low-side circuit unit 216 and the high-side circuit unit 217 include a CMOS circuit complementarily connecting a p-channel MOSFET (PMOS) and an n-channel MOSFET (NMOS). A gate of the CMOS circuit of the low-side circuit unit 216 is connected to the H-IN and receives input of the input signal transferred from the HVIC. The source of the p-channel MOSFET of the CMOS circuit of the low-side circuit unit 216 is connected to the L-VDD and the source of the re-channel MOSFET is grounded. The low-side circuit unit 216 and the high-side circuit unit 217 may include a transmission circuit other than the CMOS circuits.
A connection point (an output terminal) between the p-channel MOSFET and the n-channel MOSFET making up the CMOS circuit of the low-side circuit unit 216 is connected to a gate of the n-channel MOSFET 211 to transfer the input signal to the level-up circuit 210. A gate of the CMOS circuit of the high-side circuit unit 217 is connected to the output unit 215 of the level-up circuit 210 to receive input of the input signal transferred from the level-up circuit 210. In the CMOS circuit (hereinafter, second CMOS circuit) of the high-side circuit unit 217, the source of a p-channel MOSFET (hereinafter, second p-channel MOSFET) 130a is connected to the H-VDD and the source of an n-channel MOSFET (hereinafter, second n-channel MOSFET) 130b is connected to the Vs. A connection point between the second p-channel MOSFET 130a and the second n-channel MOSFET 130b making up the CMOS circuit of the high-side circuit unit 217 is connected to the H-OUT to transfer the input signal to the HVIC.
When an input signal from the H-IN is input to the gate of the CMOS circuit of the low-side circuit unit 216 in the level-up circuit 210 as described above, the signal is input via the CMOS circuit of the low-side circuit unit 216 to the gate of the n-channel MOSFET 211 of the level-up circuit 210. In response to the input of this input signal, the n-channel MOSFET 211 is turned on/off and an output signal is output from the output unit 215 of the level-up circuit 210 and input to the gate of the CMOS circuit of the high-side circuit unit 217. In response to the input of this signal, the CMOS circuit of the high-side circuit unit 217 is turned on/off, and an output signal of the CMOS circuit of the high-side circuit unit 217 (a signal for which the level has been increased by the level-up circuit 210) is output from the H-OUT. This output signal is converted into a signal using the potential of the Vs terminal 111 as a reference and is input to the gate of the upper-arm IGBT 115. In response to the input of this signal, the upper-arm IGBT 115 of the half bridge circuit is turned on/off.
As depicted in FIG. 12, the level-down circuit 220 includes a p-channel MOSFET 221, a level shift resistor 222, and a diode 223. The drain of the p-channel MOSFET 221 is connected to one end of the level shift resistor 222 and the source is connected to the H-VDD. The p-channel MOSFET 221 has a built-in body diode 224 connected in anti-parallel to the p-channel MOSFET 221. A connection point between the p-channel MOSFET 221 and the level shift resistor 222 is an output unit 225 of the level-up circuit 210. The other end of the level shift resistor 222 is grounded. The diode 223 is connected in parallel to the level shift resistor 222. The diode 223 has a function of preventing the level shift resistor 222 from generating heat and being destroyed by the heat generated when the potential of the H-VDD becomes considerably lower than the potential of the GND. The diode 223 also has a function of preventing excessive voltage from being applied to a gate of a CMOS circuit of a low-side circuit unit 227 described later when overcurrent is applied to the H-VDD during on-operation of the p-channel MOSFET 221.
A high-side circuit unit 226 and the low-side circuit unit 227 are disposed upstream and downstream from the level-down circuit 220 as peripheral circuits of the level-down circuit 220. Both the high-side circuit unit 226 and the low-side circuit unit 227 include a CMOS circuit complementarily connecting a p-channel MOSFET and an re-channel MOSFET. A gate of the CMOS circuit of the high-side circuit unit 226 receives input of an alarm signal formed based on the abnormality signal 110. The source of the p-channel MOSFET of the CMOS circuit of the high-side circuit unit 226 is connected to the H-VDD and the source of the re-channel MOSFET is connected to the Vs. The low-side circuit unit 227 and the high-side circuit unit 227 may include a transmission circuit other than the CMOS circuits.
A connection point (an output terminal) between the p-channel MOSFET and the n-channel MOSFET making up the CMOS circuit of the high-side circuit unit 226 is connected to a gate of the p-channel MOSFET 221 to transfer the input signal to the level-down circuit 220. A gate of the CMOS circuit of the low-side circuit unit 227 is connected to the output unit 225 of the level-down circuit 220 to receive the input of the input signal transferred from the level-down circuit 220. In the CMOS circuit of the low-side circuit unit 227, a source of the p-channel MOSFET is connected to the L-VDD and a source of the n-channel MOSFET is grounded. A connection point between the p-channel MOSFET and the n-channel MOSFET making up the CMOS circuit of the low-side circuit unit 227 is connected to the ALM-OUT to output the output signal from the ALM-OUT to the outside.
When an alarm signal based on the abnormality signal 110 is input to the gate of the CMOS circuit of the high-side circuit unit 226 in the level-down circuit 220 as described above, the signal is input via the CMOS circuit of the high-side circuit unit 226 to the gate of the p-channel MOSFET 221 of the level-down circuit 220. In response to the input of this signal, the p-channel MOSFET 221 is turned on/off and an output signal is output from the output unit 225 of the level-down circuit 220 and input to the gate of the CMOS circuit of the low-side circuit unit 227. In response to the input of this signal, the CMOS circuit of the low-side circuit unit 227 is turned on/off, and an output signal of the CMOS circuit of the low-side circuit unit 227 (an alarm signal for which the level has been decreased by the level-down circuit 220) is output from the ALM-OUT.
A cross-sectional structure of a conventional HVIC will be described. FIG. 13 is a cross-sectional view of a conventional high-voltage integrated circuit device. Among the constituent elements of a self-isolated HVIC 200, FIG. 13 depicts main portions of the low-side circuit unit 216, the high-side circuit unit 217, the level-up circuit 210, and the level-up circuit 210 as well as a high-voltage junction termination region (HVJT) 201. An arrow continuing from the left side of a cross-sectional view depicted on the upper side to the left side of the cross-sectional view depicted on the lower side of FIG. 13 indicates that the cross-sectional view depicted on the upper side and the cross-sectional view depicted on the lower side represent one continuous p-type semiconductor substrate 101 (a semiconductor chip). An H-IN, an H-OUT, an H-VDD, an L-VDD, a Vs, and a GND are terminals respectively corresponding to the H-IN, the H-OUT, the H-VDD, the L-VDD, the Vs, and the GND of the HVIC depicted in FIG. 10.
As depicted in FIG. 13, the conventional HVIC 200 has n−-type well regions 102, 104, an n-type well region 103, and a p-type well region 105 each selectively disposed in a surface layer on a front surface of the p-type semiconductor substrate 101 connected to the GND. The n−-type well region 104 surrounds the periphery of the n-type well region 103 and the n−-type well region 102 is disposed outside (toward the periphery of the chip) the n−-type well region 104. The p-type well region 105 is disposed between the n−-type well region 102 and the n−-type well region 104 and contacts the n−-type well region 102 and the n−-type well region 104.
In the n−-type well region 102, the low-side circuit units 216, 227 that are peripheral circuits of the level shifter circuit are disposed. FIG. 13 depicts a first CMOS circuit (a p-channel MOSFET (hereinafter, first p-channel MOSFET) 120a and an n-channel MOSFET (hereinafter, first re-channel MOSFET) 120b) making up the low-side circuit unit 216. In the n-type well region 103, the level shifter circuit and the high-side circuit units 217, 226 that are peripheral circuits of the level shifter circuit are disposed. FIG. 13 depicts a second CMOS circuit (the second p-channel MOSFET 130a and the second n-channel MOSFET 130b) making up the high-side circuit unit 217.
The first p-channel MOSFET 120a includes a typical horizontal MOS gate (an insulated gate made of metal-oxide-semiconductor) structure made up of the n−-type well region 102, an n+-type contact region 122, a p+-type source region 123, a p+-type drain region 124, and a gate electrode 125, as well as a source electrode 161 and a drain electrode 162. The gate electrode 125 is connected to the H-IN. The source electrode 161 is connected to the L-VDD. The drain electrode 162 is connected to a drain electrode 164 of the first re-channel MOSFET 120b. 
The first n-channel MOSFET 120b includes a typical horizontal MOS gate structure made up of a p-type offset region 121, an n+-type drain region 126, an n+-type source region 127, a p+-type contact region 128, and a gate electrode 129, as well as a source electrode 163 and a drain electrode 164. The gate electrode 129 is connected to the gate electrode 125 of the first p-channel MOSFET 120a and is also connected to the H-IN. The source electrode 163 is connected to the GND. The drain electrode 164 is connected to the drain electrode 162 of the first p-channel MOSFET 120a. 
The second p-channel MOSFET 130a includes a typical horizontal MOS gate structure made up of the n-type well region 103, an n+-type contact region 132, a p+-type source region 133, a p+-type drain region 134, and a gate electrode 135, as well as a source electrode 165 and a drain electrode 166. The gate electrode 135 is connected to the output unit 215 of the level-up circuit 210. The level shift resistor 212 and the diode 213 are connected in parallel between the H-VDD and the output unit 215. The source electrode 165 is connected to the H-VDD. The drain electrode 166 is connected to the H-OUT.
The second n-channel MOSFET 130b includes a typical horizontal MOS gate structure made up of a p-type offset region 131, an n+-type drain region 136, an n+-type source region 137, a p+-type contact region 138, and a gate electrode 139, as well as a source electrode 167 and a drain electrode 168. The gate electrode 139 is connected to the gate electrode 135 of the second p-channel MOSFET 130a (not depicted). The source electrode 167 is connected to the Vs. The drain electrode 168 is connected to the drain electrode 166 of the second p-channel MOSFET 130a and is also connected to the H-OUT.
The n-channel MOSFET 211 making up the level-up circuit 210 is disposed from the n-type well region 103 across the n−-type well region 104 to the p-type well region 105 to contact the n−-type well region 104. The n-channel MOSFET 211 making up the level-up circuit 210 includes the n-type well region 103, the n−-type well region 104, the p-type well region 105, an n+-type source region 141, an n+-type drain region 142, a p+-type contact region 143, a gate electrode 144, a source electrode 145, and a drain electrode 146. The p-type well region 105 acts as a base region.
The n+-type source region 141 and the p+-type contact region 143 are selectively disposed inside the p-type well region 105. The n+-type drain region is selectively disposed inside the n-type well region 103. On a surface of the p-type well region 105 interposed between the n+-type source region 141 and the n−-type well region 104, the gate electrode 144 is disposed via a gate insulating film. The gate electrode 144 is connected to the drain electrode 162 of the first p-channel MOSFET 120a and the drain electrode 164 of the first n-channel MOSFET 120b. The source electrode 145 is in contact with the n+-type source region 141 and the p+-type contact region 143. The source electrode 145 is connected to the GND.
The drain electrode 146 contacts the n+-type drain region. The drain electrode 146 is connected through surface metal wiring (not depicted) to the level shift resistor 212 and is connected via the level shift resistor 212 to the H-VDD. A connection portion between the drain electrode 146 and the level shift resistor 212 is the output unit 215 of the level-up circuit 210. The output from the output unit 215 is at low and high potentials when the n-channel MOSFET 211 is turned on and off, respectively. Therefore, the HVIC 200 can perform a level shift operation that is signal transfer between different reference potentials. Reference numeral 147 denotes a p+-type contact region and reference numeral 148 denotes a pickup electrode.
The source electrode (hereinafter, first pickup electrode) 145 of the n-channel MOSFET 211 acts as a pickup electrode extracting from the p+-type contact region (hereinafter, first high-concentration region) 143, electrons injected into the p-type well region 105 at the occurrence of negative surge voltage. In a surface layer on the substrate front surface side of the n-type well region 103, an n+-type contact region (hereinafter, second high-concentration region) 151 is disposed near a boundary with the n−-type well region 104. A second pickup electrode 152 contacts the second high-concentration region 151. The second pickup electrode 152 is connected to the H-VDD and has a function of extracting from the second high-concentration region 151, holes injected into the n-type well region 103 at the occurrence of the negative surge voltage.
Bridge circuits formed by combining the half bridge circuits made up of switching power devices (the IGBTs 114, 115) using the HVIC 200 described above as a driving element are widely used not only in inverters for controlling motors but also in a number of fields such as power source applications for plasma display panels (PDPs) and liquid crystal panels and inverters for home electrical appliances including air conditioners and lighting. Other than IGBTs, power MOSFETs are used for the switching power devices making up the half bridge circuits. These motors and illuminations act as the L-load 118 as described above. Therefore, the Vs and the H-VDD of the HVIC 200 are adversely affected by parasitic inductance components, etc. due to wiring on a printed board, a cable to the L-load 118, etc.
When the upper-arm IGBT 115 is turned off, this parasitic inductance component causes the potential of the Vs terminal 111 (the reference potential of the high-side circuit units 217, 226) and the potential of the H-VDD (the potential using the potential of the Vs terminal 111 as a reference) to vary toward the negative potential side relative to the GND potential (0 V). For example, negative surge voltage VS0 having a negative potential relative to the GND potential is applied to the Vs terminal 111 when the upper-arm IGBT 115 is turned off. This negative surge voltage VS0 can be calculated by Equation (1). In Equation (1), L0 is an inductance value of the L-load 118 and l is a value of a current flowing through the IGBT 115.VS0=L0×dI/dt  (1)When the negative surge voltage VS0 applied to the Vs terminal 111 becomes lower than [GND potential−(Vsupply+Vfd)], parasitic pn diodes 171, 172 of the self-isolated HVIC 200 (chip) begins to conduct. The parasitic pn diode 171 is made up of the p-type semiconductor substrate 101 and the n-type well region 103. The parasitic pn diode 172 is made up of the p-type well region 105 and the n−-type well region 104. Vsupply is a battery voltage of the low-voltage power source 113 or between both ends of a bootstrap capacitor not depicted. Vfd is a forward voltage drop of the parasitic pn diodes 171, 172.
If the potential of the Vs terminal 111 is significantly pulled in the negative direction, overcurrent flows through the HVIC 200 (chip). This may cause malfunction or latch-up of the high-side circuit unit 217 making up the HVIC 200, resulting in breakdown or destruction of the HVIC 200. While the potential of the Vs terminal 111 is pulled in the negative direction, a spike-shaped negative surge (an abrupt surge associated with a current change) voltage VS1 (=L1×dl1/t) projecting in the negative direction is applied to the Vs terminal 111 in proportion to the product of a parasitic inductance component L1 due to wiring on a printed board, a cable to the L-load 118, etc. from the HVIC 200 and a period dl1/t required until the on-current l1 flowing through the IGBT 115 during off-time of the IGBT 115 becomes zero. For example, the negative surge voltage VS0 applied to the Vs terminal 111 in this case is about −30 V, for example, and the application period thereof is approximately several hundred to 500 ns.
A planar layout of the constituent units of the conventional HVIC 200 will be described with reference to FIGS. 13 and 14. FIG. 14 is a planar view of a planar layout of the high-voltage integrated circuit device of FIG. 13. FIG. 14 depicts the HVJT 201 including a high potential region in which the high-side circuit units 217, 226 are disposed, a low potential region in which the low-side circuit units 216, 227 are disposed, and a region (hereinafter, common potential region) to which voltage at a common potential (GND potential) is applied. As depicted in FIG. 14, the n-type well region 103 is the high potential region and the high-side circuit unit 217, an H-VDD pad, an H-OUT pad, a Vs pad, etc. are disposed therein. FIG. 14 depicts a Vs potential region 181 connected to the Vs pad and an H-VDD potential region 182 connected to an H-VDD pad.
The Vs potential region 181 is electrically connected to the Vs pad and is a region to which voltage at the potential of the Vs is applied. For example, the Vs potential region 181 corresponds to the p-type offset region 131 and the p+-type drain region 134 of the second n-channel MOSFET 130b making up a logic unit of the high-side circuit unit 217. The H-VDD potential region 182 is electrically connected to the H-VDD pad and is a region to which voltage at the potential of the H-VDD is applied. For example, the H-VDD potential region 182 is a region in which the n+-type contact region 132 and the p+-type source region 133 of the second p-channel MOSFET 130a of the high-side circuit unit 217 are disposed. The n−-type well region 104 is a breakdown voltage region and is disposed so as to surround and contact the n-type well region 103.
The second high-concentration region 151 is an n+-type contact region and is disposed in the n-type well region 103, along the perimeter of the n-type well region 103, near the boundary with the n−-type well region 104. The second high-concentration region 151 is disposed away from the n−-type well region 104. The second pickup electrode 152 is disposed on the second high-concentration region 151. The second pickup electrode 152 is connected to the H-VDD pad. The p-type well region 105 is the common potential region and is disposed to contact the n−-type well region 104 and surround the periphery of the n−-type well region 104. The first high-concentration region 143 is a p+-type contact region and is annularly disposed in the p-type well region 105 along the outer circumference of the n−-type well region 104. The first pickup electrode 145 is disposed on the first high-concentration region 143.
In FIG. 14, black squares respectively arranged as the first and second pickup electrodes 145, 152 are portions of the first and second pickup electrodes 145, 152 that are deposited on an interlayer insulating film and a protective film (not depicted) covering a chip front surface and that are embedded in contact holes. Therefore, the black squares representing the first and second pickup electrodes 145, 152 are contacts (electric contact portions) with the first and second high-concentration regions 143, 151. Although not depicted in FIG. 14, the first and second pickup electrodes 145, 152 are annularly arranged on the first and second high-concentration regions 143, 151, respectively. The HVJT 201 is made up of the first and second high-concentration regions 143, 151 as well as the n-type well region 103, the p-type well region 105, and the n−-type well region 104 interposed between the first high-concentration region 143 and the second high-concentration region 151.
In the HVJT 201, the level shifter circuit is disposed from the n-type well region 103 across the n−-type well region 104 to the p-type well region 105 in a region including a corner portion of the n−-type well region 104 having an approximately rectangular annular shape, for example. FIG. 14 depicts the n+-type drain region 142, the gate electrodes 144 (144a, 144b), and the drain electrode 146 of the n-channel MOSFET 211 of the level-up circuit 210. The n-channel MOSFET 211 makes up a reset-set (RS) flip-flop retaining a state in which the output signal (gate signal) of the IGBT 115 is reset to a low level or set to a high level.
The n-type well region 103 has a planar shape of an approximately recessed square having one corner portion recessed inward (toward a chip center portion) and the n+-type drain region 142 is disposed in the n−-type well region 104 in a recessed portion of the n-type well region 103. The drain electrode 146 is disposed on the n+-type drain region 142. Although not depicted, the n+-type drain region 142 and the drain electrode 146 are disposed for each of the setting and resetting n-channel MOSFETs 211. The gate electrodes 144a, 144b receiving inputs of set and reset signals are disposed in the n−-type well region 104 and the p-type well region 105. The gate electrodes 144a, 144b are respectively disposed on straight line portions corresponding to two sides sharing one corner portion of the approximately rectangular annular p-type well region 105.
The n−-type well region 102 is the low potential region and is disposed around the p-type well region 105 to contact the p-type well region 105 and surround the periphery of the p-type well region 105. The n−-type well region 102 has a logic unit (not depicted) of the low-side circuit unit 216, a GND pad, an H-IN pad, and an L-VDD pad disposed therein. In FIG. 14, dashed lines surrounding the pads indicate regions into which current flowing through a parasitic pn diode flows (similarly with respect to FIGS. 1 and 3 to 5). A region indicated by dotted lines (dotted lines surrounding a portion of the second high-concentration region 151 and contacting with the H-VDD pad) is a wiring layer connecting the drain electrode 146 and the second pickup electrode 152 of the re-channel MOSFET 211 with the H-VDD pad.
If the conventional HVIC 200 is reduced in chip size by efficiently arranging the Vs potential region 181 and the H-VDD potential region 182 without waste, the Vs potential region 181 is disposed near the periphery of the n-type well region 103 in proximity to the second high-concentration region 151 of the HVJT 201. Therefore, one side 185 of the approximately rectangular Vs potential region 181 is parallel to and faces one inner peripheral side of the approximately rectangular annular second high-concentration region 151 surrounding the periphery of the n-type well region 103. As a result, the distance between the Vs potential region 181 and the HVJT 201 can be minimized on the one side (hereinafter, facing position) 185 of the second high-concentration region 151 facing the Vs potential region 181.
To protect such an HVIC driving a half-bridge type power transistor in anticipation of an excessive negative swing (application of negative serge voltage) at an output node, a circuit has been proposed that includes a resistor connected in series with a parasitic diode on the HVIC chip and disposed between a substrate and a ground potential terminal of the HVIC chip so as to limit current in a negative voltage spike (a negative surge) flowing through the parasitic diode of the HVIC due to a negative voltage transient phenomenon at the output node (see, e.g., Japanese Patent No. 3346763).
As another HVIC, a device has been proposed that diminishes an adverse effect of a negative voltage (an reverse bias) applied at a level exceeding the rated breakdown voltage, by inserting a diode between a drain electrode of a switching element belonging to a level shifter circuit and a gate electrode of a MOS transistor belonging to an amplifier (a CMOS circuit) (see, e.g., Japanese Laid-Open Patent Publication No. 2001-25235). In Japanese Laid-Open Patent Publication No. 2001-25235, the operation of the amplifier is prevented from being adversely affected by current flowing backward through the switching element.
As another HVIC, a device has been proposed that has a level shift resistor, a current-limiting resistor, and a switching element (with a drain on the high potential side) making up a level-up circuit connected in this order in series from a high voltage side of a high-voltage power source between the high potential side and the low potential (ground potential) side of the high-voltage power source so as to use a portion between the level shift resistor and the current-limiting resistor as an output unit of the level up circuit (see, e.g., Japanese Laid-Open Patent Publication No. 2008-301160). In Japanese Laid-Open Patent Publication No. 2008-301160, the current-limiting resistor is connected to a current path between the high potential side (H-VDD) and the low potential side (GND) of a level shifter circuit using a potential of a Vs terminal as a reference, thereby preventing a body diode of an n-channel MOSFET making up the level-up circuit and a parasitic pn diode itself of the HVIC from being destroyed due to overcurrent and further preventing a position with a small current capacity in the level shifter circuit from being destroyed by overcurrent.
As another HVIC, a device has been proposed that has a high-voltage diode disposed between a common grounding node and a virtual grounding (intermediate potential) node having a high-potential-side reference potential by using a common substrate region inside the HVIC (see, e.g., Japanese Laid-Open Patent Publication No. 2010-263116). In Japanese Laid-Open Patent Publication No. 2010-263116, the high-voltage diode is disposed between a terminal having the high-potential-side reference potential (Vs terminal) and the substrate region having the common ground potential (GND potential), thereby suppressing a reduction in high-potential-side power source voltage due to undershooting of negative voltage generated in the virtual grounding node at the high-potential-side reference potential.
As another HVIC, a device has been proposed that has a planar layout with a double RESURF structure partially added by thinning contacts of an HVJT at a position close to a high-potential-side reference potential region (a Vs potential region) or by widening a width of a breakdown voltage region making up the HVJT (see, e.g., WO 2012/176347). In WO 2012/176347, a reduction is achieved in a carrier injection amount in the high-potential-side reference potential region associated with a reduction in high-potential-side power source voltage due to undershooting of negative voltage.
As another HVIC, a device has been proposed that has an n−-type diffusion region annularly formed as a low-voltage region in a p−-type semiconductor substrate, that has an n-type diffusion region making up an HVJT annularly formed contacting the inside thereof, and that has an island-shaped n-type diffusion region disposed further inside thereof as a high-voltage region across a predetermined width of the p−-type semiconductor substrate (see, e.g., Japanese Patent No. 3917211 (paragraph 0045, FIG. 8)). In the structure proposed in Japanese Patent No. 3917211, an n-type diffusion layer making up the HVJT and an n-type diffusion layer disposed with a high-side circuit unit are separated by an annular p−-type diffusion layer.